R8C/13 Group
6. Clock Generating Circuit
System clock control register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
After reset
6816
0
0
1
0 0
Bit symbol
Bit name
Reserved bit
Function
RW
RW
Set to “0”
(b1-b0)
CM02
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode
RW
RW
RW
RW
Reserved bit
Set to “1”
(b3)
Reserved bit
Set to “0”
(b4)
Main clock (XIN-XOUT)stop 0 : On
(2, 4)
CM05
(3)
bit
1 : Off
CPU clock division select 0 : CM16 and CM17 valid
CM06
RW
RW
(5)
1 : Divide-by-8 mode
bit 0
Reserved bit
Set to “0”
(b7)
NOTES:
1. Set the PRC0 bit of PRCR register to “1” (write enable) before writing to this register.
2. The CM05 bit is provided to stop the main clock when the on-chip oscillator mode is selected. This bit cannot be used for detection
as to whether the main clock stopped or not. To stop the main clock, the following setting is required:
(1) Set the OCD0 and OCD1 bits in the OCD register to “00
(2) Set the OCD2 bit to “1” (on-chip oscillator clock selection).
3. Set the CM05 bit to “1” (main clock stops) and the CM13 bit in the CM1 register to “1” (XIN-XOUT pin) when the external clock is input.
4. When the CM05 bit is set to “1” (main clock stop), P4 and P4 can be used as input ports.
2” (disable oscillation stop detection function).
6
7
5. When entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide-by-8 mode).
System clock control register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
After reset
2016
0
0
Bit symbol
CM10
Bit name
Function
RW
RW
All clock stop control bit(4,7)
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Set to “0”
RW
RW
RW
(b1)
(b2)
Reserved bit
Set to “0”
0 : Input port P4
1 : XIN-XOUT pin
6, P47
Port XIN-XOUT switch bit(7)
CM13
CM14
CM15
0 : Low-speed on-chip oscillator on
1 : Low-speed on-chip oscillator off
Low-speed on-chip
oscillation stop bit(5, 6)
RW
RW
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
select bit(2)
b7 b6
CPU clock division
select bit 1(3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
CM16
CM17
RW
RW
NOTES:
1. Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
2. When entering stop mode from high or middle speed mode, the CM15 bit is set to “1” (drive capacity high).
3. Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
4. If the CM10 bit is “1” (stop mode), the internal feedback resistor becomes ineffective.
5. The CM14 bit can be set to “1” (low-speed on-chip oscillator off) if the OCD2 bit=0 (main clock selected). When the OCD2 bit is
set to “1” (selecting on-chip oscillator clock), the CM14 bit is set to “0” (low-speed on-chip oscillator on). This bit remains
unchanged when “1” is written.
6. When using voltage detection interrupt circuit, CM14 bit is set to “0”
7. When the CM10 bit is set to “1” (stop mode) or the CM05 bit in the CM0 register to “1” (main clock stops) and the CM13 bit is set
to “1” (XIN-XOUT pin), the XOUT (P4
When the CM13 bit is set to
“0
” (input ports
P4
7
) pin becomes “H”.
P4 ) the
P4
7 (X
OUT) enters input mode
6
7
Figure 6.2 CM0 Register and CM1 Register
Rev.1.20 Jan 27, 2006 page 31 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
