R8C/13 Group
17.4 CPU Rewrite Mode
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1
Address
01B516
After reset
1000000X
2
0
0
1
0
Bit symbol
Bit name
Function
RW
RO
When read, its content is
indeterminate.
Reserved bit
(b0)
EW1 mode select bit(1, 2)
Reserved bit
0: EW0 mode
1: EW1 mode
FMR11
RW
RW
RW
Set to “0”
(b4-b2)
FMR15
Block0 rewrite disable bit(2, 3)
0 : Rewrite enabled
1 : Rewrite disabled
Block1 rewrite disable bit(2, 3)
Reserved bit
0 : Rewrite enabled
1 : Rewrite disabled
FMR16
RW
Set to “1”
RW
(b7)
NOTES:
1. To set this bit to “1”, write “0” and then “1” (CPU rewrite mode enabled) in succession when the FMR01
bit = 1. Make sure no interrupts will occur before writing “1” after writing “0”.
2. This bit is set to “0” by setting the FMR01 bit to “0” (CPU rewrite mode disabled).
3. When the FMR01 bit is “1” (CPU rewrite mode enabled), the FMR15 and FMR16 bits are rewritable.
To set this bit to “0”, write “1” and then “0” in succession.
To set this bit to “1”, write “1”.
Flash memory control register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR4
Address
01B316
After reset
01000000
2
0
0
0
0
0
Bit symbol
FMR40
Bit name
Function
RW
RW
Erase-suspend function
enable bit(1)
0: Invalid
1: Valid
Erase-suspend request bit(2)
0: Erase restart
1: Erase suspend request
FMR41
RW
RO
Set to “0”
Reserved bit
(b5-b2)
FMR46
0: Disable reading
1: Enable reading
Read status flag
RO
Reserved bit
Set to “0”
(b7)
RW
NOTES:
1. To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts will occur before
writing “1” after writing “0”.
2. This bit is valid only when the FMR40 bit is set to “1” (valid) and can only be written before ending an
erase after issuing an erase command. Other than this period, this bit is set to “0”.
In EW0 mode, this bit can be set to “0” and “1” by program.
In EW1 mode, this bit is automatically set to “1” if a maskable interrupt occurs during an erase operation
while the FMR40 bit is set to “1”. This bit can not be set to “1” by program. (Can be set to “0”.)
Figure 17.4 FMR1 Register and FMR4 Register
Rev.1.20 Jan 27, 2006 page 172 of 205
REJ09B0111-0120