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R5F21134DFP 参数 Datasheet PDF下载

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型号: R5F21134DFP
PDF下载: 下载PDF文件 查看货源
内容描述: 16位单片机M16C族/ R8C / Tiny系列 [16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 224 页 / 2076 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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R8C/13 Group  
17.4 CPU Rewrite Mode  
17.4.3 Software Commands  
Software commands are described below. The command code and data must be read and written in  
8-bit units.  
Table 17.4 Software Commands  
First bus cycle  
Address  
Second bus cycle  
Address  
Command  
Data  
to D  
Data  
to D0)  
Mode  
Mode  
Read  
(D  
7
0
)
(D  
7
Write  
Write  
Write  
Write  
Write  
Read array  
X
X
FF16  
7016  
5016  
4016  
2016  
X
SRD  
Read status register  
Clear status register  
Program  
X
WA  
BA  
WD  
WA  
X
Write  
Write  
Block erase  
D016  
SRD: Status register data (D7 to D0)  
WA: Write address (Make sure the address value specified in the the first bus cycle is the same address  
as the write address specified in the second bus cycle.)  
WD: Write data (8 bits)  
BA: Given block address  
X: Any address in the user ROM area  
Read Array Command  
This command reads the flash memory.  
Writing FF16in the first bus cycle places the microcomputer in read array mode. Enter the read  
address in the next or subsequent bus cycles, and the content of the specified address can be read  
in 8-bit units.  
Because the microcomputer remains in read array mode until another command is written, the con-  
tents of multiple addresses can be read in succession.  
Read Status Register Command  
This command reads the status register.  
Write 7016in the first bus cycle, and the status register can be read in the second bus cycle. (Refer  
to Section 17.4.4, Status Register.) When reading the status register too, specify an address in the  
user ROM area.  
Avoid executing this command in EW1 mode.  
Clear Status Register Command  
This command sets the status register to 0.  
Write 5016in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5  
in the status register will be set to 0.  
Rev.1.20 Jan 27, 2006 page 175 of 205  
REJ09B0111-0120  
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