M66291GP 参数 Datasheet PDF下载

M66291GP/HP

1.2.1

USB-IP

The USB-IP block contains a serial interface engine, a transfer controller, an endpoint controller, a FIFO

memory controller, an interrupt controller, and a CPU interface register.

(1) Serial Interface Engine (SIE)

The serial interface engine (SIE) executes low-order protocols processing of USB as follows:

•

Extracts receive data/clock and generates transmit clock

•

Serial - parallel conversion of transmit/receive data

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NRZI (Non Return Zero Invert) encoding and decoding

•

Bit stuffing and destuffing

•

SYNC (Synchronization pattern) and EOP (End Of Packet) detection

•

USB address and endpoint detection

•

CRC (Cyclic Redundancy Check) generation and checking

(2) Transfer Controller

The transfer controller executes device state transition control and control transfer sequence control.

(3) Endpoint Controller

The endpoint controller executes status control per endpoint.

(4) FIFO Memory Controller

The FIFO memory controller controls the write/read of the transmit/receive data at SIE (USB bus) side and

internal bus (CPU bus) side under state control by the endpoint controller.

(5) Interrupt Controller

The interrupt controller outputs the status signals outputted by transfer controller and endpoint controller to

INT0, INT1/SOF interrupt pins according to the CPU interface register setting.

(6) CPU Interface Register

The CPU interface register block is composed of the registers for mode setting, command setting and status

reading.

1.2.2

Bus Interface Unit (BIU)

The bus interface unit (BIU) is a circuit to conform USB-IP to LSI external bus.

1.2.3

FIFO Memory

The FIFO memory is a FIFO for endpoint transmit/receive. It is possible to set 6 endpoints EP1 to EP6 in

addition to EP0, the endpoint for control transfer.

1.2.4

I/O Block

The I/O block is composed of USB transceiver, oscillation buffer, 48 MHz PLL, Vbus input circuit and D+ pin

pullup control circuit.

Rev1.01

2004.11.01

page 5 of 122