MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
READY, HOLD TIMING
Timing requirements (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit = “0” , unless
otherwise noted)
The rise and fall time of input signal must be 100 ns or less respectively, unless otherwise noted.
Limits
Symbol
Parameter
Unit
Min.
42
42
0
Max.
tsu(RDY-φ1)
tsu(HOLD-φ1)
th(φ1-RDY)
RDY input setup time
HOLD input setup time
RDY input hold time
HOLD input hold time
ns
ns
ns
ns
th(φ1-HOLD)
0
: f(XIN) = 20 MHz when the clock source select bit = “1”.
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 40 MHz when the clock source select bit =
“0” , unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Max.
50
td(φ1-HLDA)
HLDA output delay time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
pxz(HLDA-RDZ)
Floating start delay time (at hold state)
Floating start delay time (at hold state)
50
pxz(HLDA-WRZ)
50
pxz(HLDA-BHEZ) Floating start delay time (at hold state)
Floating start delay time (at hold state)
50
pxz(HLDA-AZ)
50
t
pxz(HLDA-DLZ/DHZ) Floating start delay time (at hold state)
50
t
t
t
t
pzx(HLDA-RDZ)
Floating release delay time (at hold state)
Floating release delay time (at hold state)
0
0
0
0
0
pzx(HLDA-WRZ)
pzx(HLDA-BHEZ) Floating release delay time (at hold state)
Floating release delay time (at hold state)
pzx(HLDA-AZ)
t
pzx(HLDA-DLZ/DHZ) Floating release delay time (at hold state)
: f(XIN) = 20 MHz when the clock source select bit = “1”.
87
RENESAS [ RENESAS TECHNOLOGY CORP ]
