MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B input (Count input in event counter mode)
Symbol
Limits
Parameter
Unit
Min.
80
Max.
tc(TB)
TBiIN input cycle time (one edge count)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edge count)
40
40
160
80
tw(TBH)
tw(TBL)
TBiIN input high-level pulse width (both edge count)
TBiIN input low-level pulse width (both edge count)
80
Timer B input (Pulse period measurement mode)
Symbol Parameter
Limits
Unit
ns
ns
ns
ns
ns
ns
Min.
16 × 109
f(XIN)
8 × 109
f(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
Max.
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
(400)
tc(TB)
TBiIN input cycle time
(320)
(200)
(160)
(200)
(160)
tw(TBH)
tw(TBL)
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN) ≤ 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) ≤ 25 MHz). At this time, the clock source select bit is “0.”
Timer B input (Pulse width measurement mode)
Limits
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
Min.
16 × 109
f(XIN)
8 × 109
f(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
8 × 109
f(XIN)
4 × 109
f(XIN)
Max.
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
f(XIN) ≤ 40 MHz
f(XIN) ≤ 25 MHz
(400)
(320)
(200)
(160)
(200)
(160)
tc(TB)
TBiIN input cycle time
tw(TBH)
tw(TBL)
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Note : The TBiIN input cycle time requires 4 or more cycles of count source. The TBiIN input high-level pulse width and the TBiIN input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(XIN)/4 in high-speed running
(f(XIN) ≤ 40 MHz) and when the count source is f(XIN)/2 in low-speed running (f(XIN) ≤ 25 MHz). At this time, the clock source select bit is “0.”
A-D trigger input
Limits
Symbol
Parameter
Unit
Min.
1000
125
Max.
tc(AD)
tw(ADL)
ADTRG input cycle time (minimum allowable trigger)
ADTRG input low-level pulse width
ns
ns
85
RENESAS [ RENESAS TECHNOLOGY CORP ]
