MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (VCC = 5 V±10 %, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz when the clock source select bit = “0” ,
unless otherwise noted)
Memory expansion and Microprocessor mode : Low-speed running
2-φ access
3-φ access
4-φ access
Symbol
Parameter
Unit
Min. Max. Min. Max. Min. Max.
tw(φH), tw(φL)
td(φ1–WR)
φ high-level pulse width, φ low-level pulse width (Note)
20
–7
–7
60
60
15
15
8
20
–7
–7
140
140
15
15
8
20
–7
–7
140
140
95
95
55
95
95
55
95
95
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
___
WR output delay time
12
12
12
12
12
12
td(φ1–RD)
__
tw(WR)
__
RD output delay time
___
WR low-level pulse width (Note)
RD low-level pulse width (Note)
Address output delay time (Note)
Address output delay time (Note)
tw(RD)
td(A–WR)
td(A–RD)
td(A–ALE)
Address output delay time (Note)
____
td(BHE–WR)
td(BHE–RD)
td(BHE–ALE)
td(CS–WR)
td(CS–RD)
td(CS–ALE)
BHE output delay time (Note)
15
15
8
15
15
8
____
BHE output delay time (Note)
____
BHE output delay time (Note)
Chip select output delay time (Note)
Chip select output delay time (Note)
Chip select output delay time (Note)
Data output delay time
15
15
8
15
15
8
td(WR–DLQ/DHQ)
35
30
35
30
35
30
tpxz(WR–DLZ/DHZ)
Floating start delay time (Note)
ALE output delay time
td(ALE–WR)
td(ALE–RD)
tw(ALE)
4
4
4
4
4
4
ALE output delay time
ALE pulse width (Note)
22
10
10
10
10
10
10
15
0
22
10
10
10
10
10
10
15
0
62
10
10
10
10
10
10
15
0
th(WR–A)
Address hold time (Note)
th(RD–A)
Address hold time (Note)
th(WR–BHE)
th(RD–BHE)
th(WR–CS)
th(RD–CS)
BHE hold time (Note)
BHE hold time (Note)
Chip select hold time (Note)
Chip select hold time (Note)
Data hold time (Note)
th(WR–DLQ/DHQ)
tpzx(WR–DLZ/DHZ)
Floating release delay time
Address output delay time (Note)
Address output delay time (Note)
Address output delay time (Note)
Address hold time
td(LA–WR)
12
12
5
12
12
5
92
92
52
25 (Note)
td(LA–RD)
td(LA–ALE)
th(ALE–LA)
tpxz(RD–DLZ)
tpzx(RD–DLZ)
td(WR–PiQ)
9
9
Floating start delay time
5
5
5
Floating release delay time (Note)
Port Pi data output delay time (i = 4—9, 11)
18
18
18
60
60
60
: f(XIN) = 12.5 MHz when the clock source selet bit = “1”
Note: Since the values depend on external clock input frequency f(XIN), calculate them using the bus timing data formula on the next page.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
