MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
SCL
PIN
IICIRQ
Fig. 57. Interrupt Request Signal Generation Timing
(6) START Condition Generation Method
2
When the ESO bit of the I C control register (address 00F916) is “1,”
2
execute a write instruction to the I C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 58 for the START condition gen-
eration timing diagram, and Table 8 for the START condition/STOP
condition generation timing table.
I2C status register
write signal
SCL
Setup
time
Hold time
SDA
Set time for
BB flag
BB flag
Setup
time
Fig. 58. START Condition Generation Timing Diagram
(7) RESTART Condition Generation Method
To generate the RESTART condition, take the following sequence:
2
1Set “2016” to the I C status register (S1).
2
2Write a transmit data to the I C data shift register.
2
3Set “F016” to the I C status register (S1) again.
<Example of Setting of RESTART Condition>
2
I C status register
; S1 = 2016
2
I C data shift register ; S0 = transmit data after restart
2
I C status register
; S1 = F016
60
RENESAS [ RENESAS TECHNOLOGY CORP ]
