MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ Bit 6: Communication Mode Specification Bit (transfer direction
■ Bit 7: Communication Mode Specification Bit (master/slave speci-
fication bit: MST)
specification bit: TRX)
This bit decides the direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a trans-
mitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output into the
SDA in synchronization with the clock generated on the SCL.
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are re-
ceived, and data communication is performed in synchronization with
the clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
2
When the ALS bit of the I C control register (address 00F916) is “0”
in the slave reception mode is selected, the TRX bit is set to “1”
__
(transmit) if the least significant bit (R/W bit) of the address data trans-
__
mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is
“0,” the TRX bit is cleared to “0” (receive).
The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when ar-
•
The TRX bit is cleared to “0” in one of the following conditions.
bitration lost is detected
When arbitration lost is detected.
•
When a STOP condition is detected.
•
When a STOP condition is detected.
•
When occurence of a START condition is disabled by the START
•
When occurence of a START condition is disabled by the START
•
condition duplication preventing function (Note).
condition duplication prevention function (Note).
At reset
•
With MST = “0” and when a START condition is detected.
•
With MST = “0” and when ACK non-return is detected.
•
Note: The START condition duplication prevention function disables
the START condition generation, reset of bit counter reset,
and SCL output, when the following condition is satisfied:
• a START condition is set by another master device.
At reset
•
2
I C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00F816
]
B
Name
Functions
After reset R W
0
Indeterminate
Last receive bit (LRB)
(See note)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
R —
1
2
General call detecting flag
(AD0) (See note)
0 : No general call detected
1 : General call detected
0
R —
Slave address comparison
flag (AAS) (See note)
0 : Address mismatch
1 : Address match
0
R —
3
4
5
Arbitration lost detecting flag 0 : Not detected
0
R —
(AL) (See note)
1 : Detected
I2C-BUS interface interrupt
request bit (PIN)
0 : Interrupt request issued
1 : No interrupt request issued
0
R —
Bus busy flag (BB)
0 : Bus free
1 : Bus busy
0
R W
6, 7 Communication mode
specification bits
b7 b6
0
R W
0
0 : Slave recieve mode
(TRX, MST)
0
1
1
1 : Slave transmit mode
0 : Master recieve mode
1 : Master transmit mode
Note : These bits and flags can be read out, but cannnot be written.
2
Fig. 56. I C Status Register
59
RENESAS [ RENESAS TECHNOLOGY CORP ]
