MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
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(10) Address Data Communication
➆ Set transmit data in the I C data shift register (address 00F616).
At this time, an SCL and an ACK clock automatically occurs.
➇ When transmitting control data of more than 1 byte, repeat step
➆.
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
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➀7-bit addressing format
➈ Set “D016” in the I C status register (address 00F816). After this,
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
if ACK is not returned or transmission ends, a STOP condition will
be generated.
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I C control register (address 00F916) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order
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7-bit slave address stored in the I C address register (address
(12) Example of Slave Reception
00F716). At the time of this comparison, address comparison of
An example of slave reception in the high-speed clock mode, at the
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the RBW bit of the I C address register (address 00F716) is not
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
made. For the data transmission format when the 7-bit address-
ing format is selected, refer to Figure 61, (1) and (2).
➁10-bit addressing format
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➀ Set a slave address in the high-order 7 bits of the I C address
register (address 00F716) and “0” in the RBW bit.
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516”
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I C control register (address 00F916) to “1.” An address compari-
in the I C clock control register (address 00FA16).
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son is made between the first-byte address data transmitted from
➂ Set “1016” in the I C status register (address 00F816) and hold
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the master and the 7-bit slave address stored in the I C address
the SCL at the HIGH.
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register (address 00F716). At the time of this comparison, an ad-
➃ Set a communication enable status by setting “4816” in the I C
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dress comparison between the RBW bit of the I C address regis-
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control register (address 00F916).
ter (address 00F716) and the R/W bit which is the last bit of the
➄ When a START condition is received, an address comparison is
made.
address data transmitted from the master is made. In the 10-bit
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addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
➅ •When all transmitted addresses are “0” (general call) :
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AD0 of the I C status register (address 00F816) is set to “1” and
an interrupt request signal occurs.
When the first-byte address data matches the slave address, the
•When the transmitted addresses match the address set in ➀:
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AAS bit of the I C status register (address 00F816) is set to “1.” After
AAS of the I C status register (address 00F816) is set to “1” and
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the second-byte address data is stored into the I C data shift register
an interrupt request signal occurs.
•In the cases other than the above :
(address 00F616), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
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AD0 and AAS of the I C status register (address 00F816) are
set to “0” and no interrupt request signal occurs.
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the I C address register (address 00F716) to “1” by software. This
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➆ Set dummy data in the I C data shift register (address 00F616).
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
➇ When receiving control data of more than 1 byte, repeat step ➆.
➈ When a STOP condition is detected, the communication ends.
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of the I C address register (address 00F716). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 61, (3) and (4).
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
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➀ Set a slave address in the high-order 7 bits of the I C address
register (address 00F716) and “0” in the RBW bit.
➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in
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the I C clock control register (address 00FA16).
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➂ Set “1016” in the I C status register (address 00F816) and hold
the SCL at the HIGH.
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➃ Set a communication enable status by setting “4816” in the I C
control register (address 00F916).
➄ Set the address data of the destination of transmission in the high-
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order 7 bits of the I C data shift register (address 00F616) and set
“0” in the least significant bit.
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➅ Set “F016” in the I C status register (address 00F816) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
