MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
■ Bit 4: Data Format Selection Bit (ALS)
(4) I C Control Register
2
The I C control register (address 00F916) controls the data commu-
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
nication format.
■ Bits 0 to 2: Bit Counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
2
eral call (refer to “(5) I C Status Register,” bit 1) is received, trans-
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
2
■ Bit 3: I C Interface Use Enable Bit (ESO)
■ Bit 5: Addressing Format Selection Bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
2
This bit enables usage of the multimaster I C BUS interface. When
this bit is set to “0,” the use disable status is provided, so the SDA
and the SCL become high-impedance. When the bit is set to “1,” use
of the interface is enabled.
2
the high-order 7 bits (slave address) of the I C address register (ad-
dress 00F716) are compared with address data. When this bit is set
2
When ESO = “0,” the following is performed.
to “1,” the 10-bit addressing format is selected, all the bits of the I C
2
PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I C
address register are compared with address data.
•
2
status register at address 00F816 ).
■ Bits 6 and 7: Connection Control Bits between I C-BUS Interface
2
Writing data to the I C data shift register (address 00F616) is dis-
and Ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 55).
•
abled.
“0”
“1” BSEL0
SCL1/P1
SCL2/P1
1
2
“0”
“1” BSEL1
SCL
Multi-master
“0”
“1” BSEL0
I2C-BUS
interface
SDA1/P1
SDA2/P1
3
4
“0”
“1” BSEL1
SDA
2
Note: When using multi-master I C-BUS interface, set bits 3 and
4 of the serial I/O mode register (address 021316) to “1.”
Moreover, set the corresponding direction register to “1” to
2
use the port as multi-master I C-BUS interface.
Fig. 54. Connection Port Control by BSEL0 and BSEL1
56
RENESAS [ RENESAS TECHNOLOGY CORP ]
