MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(9) START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in Figure
52 and Table 9. Only when the 3 conditions of Table 9 are satisfied,
a START/STOP condition can be detected.
(8) STOP Condition Generation Method
2
When the ES0 bit of the I C control register (address 00F916) is “1,”
2
execute a write instruction to the I C status register (address 00F816)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A
STOP condition will then be generated. The STOP condition genera-
tion timing and the BB flag reset timing are different in the standard
clock mode and the high-speed clock mode. Refer to Figure 51 for
the STOP condition generation timing diagram, and Table 8 for the
START condition/STOP condition generation timing table.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated
to the CPU.
I2C status register
write signal
SCL release time
SCL
Setup
Hold time
Hold time
time
SCL
Setup
time
SDA
Hold time
(START condition)
Setup
time
SDA
Reset time for
BB flag
SDA
(STOP condition)
BB flag
Fig. 59. STOP Condition Generation Timing Diagram
Fig. 60. START Condition/STOP Condition Detect Timing
Diagram
Table 8. START Condition/STOP Condition Generation Timing
Table
Table 9. START Condition/STOP Condition Detect Conditions
Standard Clock Mode
High-speed Clock Mode
1.0 µs (4 cycles) < SCL
Item
Setup time
Hold time
Standard Clock Mode
5.0 µs (20 cycles)
5.0 µs (20 cycles)
High-speed Clock Mode
2.5 µs (10 cycles)
6.5 µs (26 cycles) < SCL
release time
release time
2.5 µs (10 cycles)
3.25 µs (13 cycles) < Setup time 0.5 µs (2 cycles) < Setup time
3.25 µs (13 cycles) < Hold time 0.5 µs (2 cycles) < Hold time
Set/reset time
for BB flag
3.0 µs (12 cycles)
1.5 µs (6 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses de-
notes the number of φ cycles.
Note: Absolute time at φ = 4 MHz. The value in parentheses de-
notes the number of φ cycles.
61
RENESAS [ RENESAS TECHNOLOGY CORP ]
