MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Figure 19 shows the structure of the data slicer control registers.
7
0
7
0
Data slicer control register 1
(DSC1: address 00EA16)
Data slicer control register 2
(DSC2: address 00EB16)
0
0
0
0
0
0
Data slicer control bit
0: Data slicer stopped
1: Data slicer operating
Timing signal generating circuit
control bit
0: Stopped
1: Operating
Field to be sliced data selection bit
Reference clock source selection
bit
Field of main data
slice line
Field for setting
reference voltage
b2 b1
0: Video signal
1: HSYNC signal
0
0
1
1
0
1
0
1
F2
F1
F2
F1
F2
F1
F1 and F2
F1 and F2
Test bit: read-only
Fix these bits to “0.”
Fix these bits to “0.”
Field determination flag
sep
0 : H
V-pulse shape determination flag
0: Match
1: Mismatch
sep
V
sep
1 : H
Fix this bit to “0.”
Test bit: read-only
sep
V
Fix this bit to “0.”
Data latch completion flag for caption
data in main data slice line
0: Data is not yet latched
1: Data is latched
7
0
Data slicer control register 3
(DSC3: address 021016)
Definition of fields 1 (F1) and 2 (F2)
Line selection bit for slice voltage
0: Main data slice line
1: Sub-dataslice line
sep
F1 : H
SYNC
V
Field to be sliced data selection bit
Field of sub-data Field for setting
sep
V
sep
F2 : H
b2 b1
slice line
F2
reference voltage
0
0
1
1
0
1
0
1
F2
F1
F2
F1
SYNC
V
F1
F1 and F2
F1 and F2
sep
V
Setting bit of sub-data slice line
Fig. 20. Structure of data slicer control registers
27
RENESAS [ RENESAS TECHNOLOGY CORP ]
