MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
When the data slicer function is not used, the data slicer circuit can
DATA SLICER
be cut off by setting bit 0 of the data slicer control register 1 (address
00EA16) to “0.” Also, the timing signal generating circuit can be cut
off by setting bit 0 of data slicer control register 2 (address 00EB16)
to “0.” These settings can realize the low-power dissipation.
The M37270MF-XXXSP includes the data slicer function for the
closed caption decoder (referred to as the CCD). This function takes
out the caption data superimposed in the vertical blanking interval of
a composite video signal. A composite video signal which makes
the sync chip’s polarity negative is input to the CVIN pin.
0.1 F
Composite
video
signal
470
1 k
15 k
Sync pulse counter
register
560 pF
Hundred of kiloohms
to 1 M
200 pF
1 F
(address 020F16
)
CVIN
H
SYNC
HLF
RVCO
Clock run-in register 2
(address 00E716
1 0 0 1 1 1
)
Synchronizing
signal counter
Clamping
circuit
Data slicer control register 2
(address 00EB16
0 0
)
0
Synchronizing
separation
circuit
Low-pass
filter
Sync slice
circuit
Data slicer control register 1
(address 00EA16
0 0
)
Timing signal
generating
circuit
0
Data slicer ON/OFF
Window register
(address 00E216
0 0
)
V
HOLD
Reference
voltage
generating
circuit
+
–
Clock run-in
determination
circuit
1000 pF
0 1 0 1
Clock run-in register 1
(address 00E616
Comparator
Data slice line
)
specification
circuit
Data slicer control
register 3
1 0 0
Caption position register
(address 00E016
(address 021016
)
)
Start bit detecting
circuit
Clock run-in detect
register 3
Start bit position register
(address 00E116
(address 020816
)
)
Data clock
generating circui
Clock run-in
register 3
t
(address 0209 16
)
Clock run-in detect register 1
(address 00E816
)
External circui
t
16-bit shift register
Note : Make the length of wiring which
is connected to VHOLD, HLF,
RVCO and CVIN pin as short as
possible so that a leakage
high-order
low-order
Clock run-in detect register 2
(address 00E916
Data register 2
(address 00E516
)
)
current may not be generated
when mounting a resistor or a
capacitor on each pin.
Data register 1
(address 00E416
Data slicer
interrupt
request
)
Interrupt request
generating circui
Data register 4
t
(address 00ED16
)
Sync slice register 3
(address 00E316
)
Data register 3
(address 00EC16
)
0 0 0 0 1 0 1
Data bus
Fig. 19. Data slicer block diagram
26
RENESAS [ RENESAS TECHNOLOGY CORP ]
