MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(7) Internal Operation
(6) Conversion Method
➀Set bit 7 of the interrupt interval determination control register (ad-
dress 021216) to “1” to generate an interrupt request at comple-
tion of A-D conversion.
At the time when the A-D conversion starts, the following operations
are automatically performed.
➀ The A-D conversion register is set to “0016.”
➁ Set the A-D conversion • INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion • INT3 inter-
rupt bit is not set to “0” automatically).
➁ The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “Vref” is input to the comparator.
At this point, Vref is compared with the analog input voltage “VIN .”
➂ Bit 7 is determined by the comparison result as follows.
When Vref < VIN : bit 7 holds “1”
➂ When using A-D conversion interrupt, enable interrupts by setting
A-D conversion • INT3 interrupt request bit to “1” and setting the
interrupt disable flag to “0.”
When Vref > VIN : bit 7 becomes “0”
➃ Set the VCC connection selection bit to “1” to connect VCC to the
resistor ladder.
With the above operations, the analog value is converted into a digi-
tal value. The A-D conversion terminates in a maximum 50 machine
cycles (12.5µs at f(XIN) = 8 MHz) after it starts, and the conversion
result is stored in the A-D conversion register.
➄ Select analog input pins by setting the analog input selection bit of
the A-D control register.
➅ Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion regis-
ter during the A-D conversion.
An A-D conversion interrupt request occurs at the same time of A-D
conversion completion, the A-D conversion • INT3 interrupt request
bit becomes “1.” The A-D conversion completion bit also becomes
“1.”
➆ Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, that (“1”) of A-D conversion• INT3
interrupt bit, or the occurrence of an A-D conversion interrupt.
➇ Read the A-D conversion register to obtain the conversion results.
Table 2. Expression for Vref and VREF
A-D conversion register contents “n”
Vref (V)
(decimal notation)
Note : When the ladder resistor is disconnect from VCC, set the VCC
connection selection bit to “0” between steps ➆and ➇.
0
0
1
255
VREF ✕(n – 0.5)
to
256
Note: VREF indicates the voltage of internal VCC.
Contents of A-D conversion register
Reference voltage (Vref) [V]
A-D conversion start
0 0 0 0 0 0 0 0
0
VREF
2
VREF
2
VREF
2
VREF
512
VREF
4
VREF
4
1
0 0 0 0 0 0 0
1st comparison start
2nd comparison start
3rd comparison start
–
±
±
VREF
512
VREF
8
1 1 0 0 0 0 0 0
1 2 1 0 0 0 0 0
–
±
VREF
512
–
VREF
2
VREF
4
VREF
8
.....
±
±
–
±
1 2 3 4 5 6 7 1
8th comparison start
VREF
512
VREF
256
.......
±
A-D conversion completion
(8th comparison completion)
1 2
4 5 6 7 8
3
Digital value corresponding to
analog input voltage.
m : Value determined by mth (m = 1 to 8) result
Fig. 17. Changes in A-D conversion register and comparison voltage during A-D conversion
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RENESAS [ RENESAS TECHNOLOGY CORP ]
