M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
8.6.8 START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in
Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table
8.6.3 are satisfied, a START/STOP condition can be detected.
8.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats are described below.
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” is generated to the
CPU.
(1) 7-bit addressing format
To support the 7-bit addressing format, set the 10BIT SAD bit of the
2
I C control register (address 00DA16) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order 7-
2
bit slave address stored in the I C address register (address 00D816).
At the time of this comparison, address comparison of the RBW bit of
2
the I C address register (address 00D816) is not made. For the data
transmission format when the 7-bit addressing format is selected,
refer to Figure 8.6.12, (1) and (2).
SCL release time
SCL
Setup
Hold time
time
SDA
(2) 10-bit addressing format
(START condition)
Setup
To support the 10-bit addressing format, set the 10BIT SAD bit of the
Hold time
time
2
I C control register (address 00DA16) to “1.” An address comparison
SDA
(STOP condition)
is made between the first-byte address data transmitted from the
2
master and the 7-bit slave address stored in the I C address register
(address 00D816). At the time of this comparison, an address com-
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Dia-
gram
2
parison is performed between the RBW bit of the I C address regis-
____
ter (address 00D816) and the R/W bit, which is the last bit of the
address data transmitted from the master. In the 10-bit addressing
____
mode, the R/W bit not only specifies the direction of communication
for control data but is also processed as an address data bit.
When the first-byte address data matches the slave address, the
Table 8.6.3 START Condition/STOP Condition Detect Conditions
Standard Clock Mode
High-speed Clock Mode
2
AAS bit of the I C status register (address 00D916) is set to “1.” After
6.5 µs (26 cycles) < SCL
1.0 µs (4 cycles) < SCL
2
the second-byte address data is stored into the I C data shift register
release time
release time
(address 00D716), perform an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd byte matches the slave address, set the RBW bit of
3.25 µs (13 cycles) < Setup time
3.25 µs (13 cycles) < Hold time
0.5 µs (2 cycles) < Setup time
0.5 µs (2 cycles) < Hold time
Note:Absolute time at φ = 4 MHz. The value in parentheses denotes the num-
ber of φ cycles.
2
the I C address register (address 00D816) to “1” by software. This
____
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
2
of the I C address register (address 00D816). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 8.6.12, (3) and (4).
Rev.1.00 Oct 01, 2002 page 40 of 110
REJ03B0134-0100Z
RENESAS [ RENESAS TECHNOLOGY CORP ]
