INT1
INT2
INT3
AD1
–
8
SDA3
SDA2
SDA1
SCL3
SCL2
SCL1
S
IN
S
CLK
S
OUT
PWM4
PWM3
PWM2
PWM1
PWM0
9 8 7 6 5 4 3 2
17 16 15 14 13 12 11 10
30 31
39 29 40 41 42 1 32
I/O port P0
I/O port P2
I/O port P3
0
, P3
1
I/O port P1
Output for display
Output port
P5
2
–P5
5
OUT
R
G
B
VSYNC
HSYNC
Rev.1.00
I/O ports P2
6
, P2
7
Input ports P3
5
-P3
7
sub-clock input
sub-clock output
X
C OUT
17
Clock input Clock output
V
CC
V
SS
CNV
SS
21
18
24
25
26
16
22
Reset input
X
C IN
XIN
XOUT FILT
RESET
Fig. 5.1 Functional Block Diagram of M37161
P3 (3)
TIM2
TIM3
5. FUNCTIONAL BLOCK DIAGRAM
M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
2003.11.25
Timer count source
selection circuit
Timer
1
T1 (8)
Timer
2
T2 (8)
Timer
3
T3 (8)
Timer
4
T4 (8)
Timer
5
T5 (8)
Timer
6
T6 (8)
Instruction
register (8)
Instruction
decoder
OSD
circuit
Control signal
Program
counter
19
20
23
27
Clock
generating
circuit
page 4 of 128
ROM
PC
L
(8)
Index
register
Data bus
ROM
correction circuit
RAM
Progam
counter
PC
H
(8)
Address bus
8-bit
arithmetic
and
logical unit
Accumulator
A (8)
Y (8)
Index
register
Processor
status
register
PS (8)
X (8)
Stack
pointer
S (8)
14-bit PWM
Multi-master I
2
C-BUS
interface
A-D
comparator
SI/O
P2 (8)
P3 (2)
8-bit
PWM
Correction
function
ROM
P0 (8)
P1 (7)
33 34 35 36 37 38
Synchronous signal input
Input port
P5
0
,P5
1
RENESAS [ RENESAS TECHNOLOGY CORP ]
