M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
8.5 SERIAL I/O
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
This microcomputer has a built-in serial I/O which can either transmit
or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 8.5.1. The synchro-
nous clock I/O pin (SCLK), and data output pin (SOUT) also function
as port P4, data input pin (SIN) also functions as port P20–P22.
Bit 3 of the serial I/O mode register (address 00EB16) selects whether
the synchronous clock is supplied internally or externally (from the
SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use the SIN
pin for serial I/O, set the corresponding bit of the port P2 direction
register (address 00C516) to “0.”
X
CIN
1/2
Data bus
X
IN
Frequency divider
1/2 1/4 1/8 1/16
1/2
1/2
CM7
SM1
Selection gate: Connect to
black side at
reset.
SM2
SM0
Synchronous
circuit
S
CM : CPU mode register
SM : Serial I/O mode register
P20
Latch
SM3
Serial I/O
interrupt request
S
CLK
Serial I/O counter (8)
MSB
P21
Latch
SM3
SM5 : LSB
S
OUT
(See note)
SIN
Serial I/O shift register (8)
SM6
8
Note : When the data is set in the serial I/O register (address 00EA16), the register functions as the serial I/O shift register.
Fig. 8.5.1 Serial I/O Block Diagram
Rev.1.00 2003.11.25 page 26 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
