MULTIJUNCTION TIMERS
10.6 TML (Input-Related 32-Bit Timer)
10
10.6.5 TML Counters
TML0 Counter (TML0CT)
TML1 Counter (TML1CT)
<Address: H’0080 03E0>
<Address: H’0080 0FE0>
b0
?
1
?
2
?
3
?
4
?
5
?
6
7
8
9
10
?
11
?
12
?
13
?
14
?
b15
?
TML0CT, TML1CT(16 high-order bits)
?
?
?
?
b16
?
17
?
18
?
19
?
20
?
21
?
22
?
23
24
25
?
26
?
27
?
28
?
29
?
30
?
b31
?
(16 low-order bits)
?
?
<After reset: Undefined>
b
Bit Name
TML0CT
Function
R
W
0–31
32-bit counter value
R(Note 1)
Note 1: If the clock source selected for the counter is not BCLK/2, do not write to this register.
Note: • This register must always be accessed wordwise (in 32 bits) beginning with the word boundary.
The TML counters are a 32-bit up-counter, which starts counting upon deassertion of the reset input signal. The
counters can be read on-the-fly.
10.6.6 TML Measure Registers
TML0 Measure 3 Register (TML0MR3)
TML0 Measure 2 Register (TML0MR2)
TML0 Measure 1 Register (TML0MR1)
TML0 Measure 0 Register (TML0MR0)
TML1 Measure 3 Register (TML1MR3)
TML1 Measure 2 Register (TML1MR2)
TML1 Measure 1 Register (TML1MR1)
TML1 Measure 0 Register (TML1MR0)
<Address: H’0080 03F0>
<Address: H’0080 03F4>
<Address: H’0080 03F8>
<Address: H’0080 03FC>
<Address: H’0080 0FF0>
<Address: H’0080 0FF4>
<Address: H’0080 0FF8>
<Address: H’0080 0FFC>
b0
?
1
?
2
?
3
?
4
5
6
7
8
9
10
11
12
?
13
?
14
?
b15
?
TML0MR3–TML0MR0, TML1MR3–TML1MR0 (16 high-order bits)
?
?
?
?
?
?
?
?
b16
?
17
?
18
?
19
?
20
?
21
?
22
?
23
24
25
?
26
?
27
?
28
?
29
?
30
?
31
?
(16 low-order bits)
?
?
<After reset: Undefined>
b
Bit Name
TML0MR3–TML0MR0, TML1MR3–TML1MR0
Notes: • These registers are a read-only register.
• These registers must always be accessed wordwise (in 32 bits) beginning with the word boundary.
Function
R
R
W
–
0–31
32-bit measure register value
The TML measure registers are a 32-bit register, which is used to latch the counter content upon event input.
The TML measure registers can only be read, and cannot be written to.
32180 Group User’s Manual (Rev.1.0)
10-135