MULTIJUNCTION TIMERS
10.5 TMS (Input-Related 16-Bit Timer)
10
<Count clock-dependent delay>
• Because the timer operates synchronously with the count clock, there is a count clock-dependent delay
from when the timer is enabled till when it actually starts operating.
Write to the enable bit
BCLK
Count clock period
Count clock
Enable
Count clock-dependent
delay
Figure 10.5.2 Count Clock-Dependent Delay
10.5.3 TMS Related Register Map
Shown below is a TMS related register map.
TMS Related Register Map
Address
+0 address
+1 address
See pages
10-130
10-130
10-130
10-130
10-130
10-129
b0
b7 b8
TMS0 Counter
(TMS0CT)
b15
H'0080 03C0
H'0080 03C2
H'0080 03C4
H'0080 03C6
H'0080 03C8
TMS0 Measure 3 Register
(TMS0MR3)
TMS0 Measure 2 Register
(TMS0MR2)
TMS0 Measure 1 Register
(TMS0MR1)
TMS0 Measure 0 Register
(TMS0MR0)
H'0080 03CA
TMS0 Control Register
(TMS0CR)
TMS1 Control Register
(TMS1CR)
|
(Use inhibited area)
H'0080 03D0
H'0080 03D2
H'0080 03D4
H'0080 03D6
H'0080 03D8
TMS1 Counter
(TMS1CT)
TMS1 Measure 3 Register
(TMS1MR3)
TMS1 Measure 2 Register
(TMS1MR2)
10-130
10-130
10-130
10-130
10-130
TMS1 Measure 1 Register
(TMS1MR1)
TMS1 Measure 0 Register
(TMS1MR0)
32180 Group User’s Manual (Rev.1.0)
10-128
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