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M32180F8TFP 参数 Datasheet PDF下载

M32180F8TFP图片预览
型号: M32180F8TFP
PDF下载: 下载PDF文件 查看货源
内容描述: 32位RISC单芯片微型计算机M32R系列M32R / ECU系列 [32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series]
分类和应用: 计算机
文件页数/大小: 839 页 / 3694 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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MULTIJUNCTION TIMERS  
10.4 TIO (Input/Output-Related 16-Bit Timer)  
10  
10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function)  
(1) Outline of TIO delayed single-shot output mode  
In delayed single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1)  
after a finite time equal to (counter set value + 1) only once and then stops.  
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the  
counter and reload 0 register, it starts counting down from the counter’s set value synchronously with the  
count clock. The first time the counter underflows, it is loaded with the reload 0 register value and continues  
counting down. The counter stops when it underflows next time.  
The F/F output waveform in delayed single-shot output mode is inverted (F/F output level changes from low  
to high or vice versa) when the counter underflows first time and next, generating a single-shot pulse wave-  
form in width of (reload 0 register set value + 1) after a finite time equal to (first set value of counter + 1) only  
once.  
An interrupt request can be generated when the counter underflows first time and next.  
The (counter set value + 1) and (reload 0 register set value + 1) are effective as count values. (For counting  
operation, see also Section 10.3.10, “Operation of TOP Delayed Single-shot Output Mode.”)  
(2) Precautions on using TIO delayed single-shot output mode  
The following describes precautions to be observed when using TIO delayed single-shot output mode.  
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,  
the former has priority so that the counter stops.  
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the  
enable bit, the latter has priority so that count is enabled.  
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the  
enable bit, the latter has priority so that count is disabled.  
• If the counter is accessed for read immediately after being reloaded pursuant to an underflow, the counter  
value temporarily reads as H’FFFF but immediately changes to (reload value – 1) at the next clock edge.  
32180 Group User’s Manual (Rev.1.0)  
10-122  
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