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M32180F8TFP 参数 Datasheet PDF下载

M32180F8TFP图片预览
型号: M32180F8TFP
PDF下载: 下载PDF文件 查看货源
内容描述: 32位RISC单芯片微型计算机M32R系列M32R / ECU系列 [32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series]
分类和应用: 计算机
文件页数/大小: 839 页 / 3694 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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MULTIJUNCTION TIMERS  
10.4 TIO (Input/Output-Related 16-Bit Timer)  
10  
10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function)  
(1) Outline of TIO single-shot output mode  
In single-shot output mode, the timer generates a pulse in width of (reload 0 register set value + 1) only once  
and then stops.  
When the timer is enabled (by writing to the enable bit in software or by external input) after setting the reload  
0 register, the counter is loaded with the content of the reload 0 register and starts counting synchronously  
with the count clock. The counter counts down and when the minimum count is reached, stops upon under-  
flow.  
The F/F output waveform in single-shot output mode is inverted (F/F output level changes from low to high or  
vice versa) at startup and upon underflow, generating a single-shot pulse waveform in width of (reload 0  
register set value + 1) only once. An interrupt request can be generated when the counter underflows.  
The count value is (reload 0 register set value + 1). (For counting operation, see also Section 10.3.9, “Opera-  
tion of TOP Single-shot Output Mode.”)  
(2) Precautions on using TIO single-shot output mode  
The following describes precautions to be observed when using TIO single-shot output mode.  
• If the counter stops due to an underflow in the same clock period as the timer is enabled by external input,  
the former has priority so that the counter stops.  
• If the counter stops due to an underflow in the same clock period as count is enabled by writing to the  
enable bit, the latter has priority so that count is enabled.  
• If the timer is enabled by external input in the same clock period as count is disabled by writing to the  
enable bit, the latter has priority so that count is disabled.  
• Because the timer operates synchronously with the count clock, a count clock-dependent delay is in-  
cluded before F/F output is inverted after the timer is enabled.  
32180 Group User’s Manual (Rev.1.0)  
10-120  
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