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M32180F8TFP 参数 Datasheet PDF下载

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型号: M32180F8TFP
PDF下载: 下载PDF文件 查看货源
内容描述: 32位RISC单芯片微型计算机M32R系列M32R / ECU系列 [32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series]
分类和应用: 计算机
文件页数/大小: 839 页 / 3694 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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INTERRUPT CONTROLLER (ICU)  
5.5 Description of Interrupt Operation  
5
Table 5.5.1 Hardware Fixed Priority Levels  
Priority  
High  
Interrupt Request Source  
ICU Vector Table Address  
ICU Type of Input Source  
TIN3–6 input interrupt request  
TIN20–29 input interrupt request  
TIN12–19 input interrupt request  
TIN0–2 input interrupt request  
TIN7–11 input interrupt request  
TMS0,1 output interrupt request  
TOP8,9 output interrupt request  
TOP10 output interrupt request  
TIO4–7 output interrupt request  
TIO8,9 output interrupt request  
TOP0–5 output interrupt request  
TOP6,7 output interrupt request  
TIO0–3 output interrupt request  
DMA0–4 interrupt request  
H'0000 0094  
H'0000 0098  
H'0000 009C  
H'0000 00A0  
H'0000 00A4  
H'0000 00A8  
H'0000 00AC  
H'0000 00B0  
H'0000 00B4  
H'0000 00B8  
H'0000 00BC  
H'0000 00C0  
H'0000 00C4  
H'0000 00C8  
H'0000 00CC  
H'0000 00D0  
H'0000 00D4  
H'0000 00D8  
H'0000 00DC  
H'0000 00E0  
H'0000 00E4  
H'0000 00E8  
H'0000 0097  
H'0000 009B  
H'0000 009F  
H'0000 00A3  
H'0000 00A7  
H'0000 00AB  
H'0000 00AF  
H'0000 00B3  
H'0000 00B7  
H'0000 00BB  
H'0000 00BF  
H'0000 00C3  
H'0000 00C7  
H'0000 00CB  
H'0000 00CF  
H'0000 00D3  
H'0000 00D7  
H'0000 00D8  
H'0000 00DF  
H'0000 00E3  
H'0000 00E7  
H'0000 00EB  
H'0000 00EF  
H'0000 00F3  
H'0000 00F7  
H'0000 00FB  
H'0000 00FF  
H'0000 0103  
H'0000 0107  
H'0000 010B  
H'0000 010F  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Edge-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Edge-recognized  
Edge-recognized  
Edge-recognized  
Edge-recognized  
Edge-recognized  
Edge-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Edge-recognized  
Edge-recognized  
Level-recognized  
Level-recognized  
Edge-recognized  
Edge-recognized  
Level-recognized  
Level-recognized  
SIO1 receive interrupt request  
SIO1 transmit interrupt request  
SIO0 receive interrupt request  
SIO0 transmit interrupt request  
A-D0 conversion interrupt request  
TID0 output interrupt request  
TOU0 output interrupt request  
DMA5–9 interrupt request  
SIO2,3 transmit/receive interrupt request H'0000 00EC  
RTD interrupt request  
H'0000 00F0  
H'0000 00F4  
H'0000 00F8  
TID1 output interrupt request  
TOU1,2 output interrupt request  
SIO4,5 transmit/receive interrupt request H'0000 00FC  
A-D1 conversion interrupt request  
TID2 output interrupt request  
TIN30–33 input interrupt request  
CAN0 transmit/receive & error interrupt  
request  
H'0000 0100  
H'0000 0104  
H'0000 0108  
H'0000 010C  
CAN1 transmit/receive & error interrupt  
request  
H'0000 0110  
H'0000 0113  
Level-recognized  
Low  
Table 5.5.2 ILEVEL Settings and Accepted IMASK Values  
ILEVEL values set  
IMASK values at which interrupts are accepted  
0 (ILEVEL = "000")  
1 (ILEVEL = "001")  
2 (ILEVEL = "010")  
3 (ILEVEL = "011")  
4 (ILEVEL = "100")  
5 (ILEVEL = "101")  
6 (ILEVEL = "110")  
7 (ILEVEL = "111")  
Accepted when IMASK is 1–7  
Accepted when IMASK is 2–7  
Accepted when IMASK is 3–7  
Accepted when IMASK is 4–7  
Accepted when IMASK is 5–7  
Accepted when IMASK is 6–7  
Accepted when IMASK is 7  
Not accepted (interrupts disabled)  
32180 Group User’s Manual (Rev.1.0)  
5-14  
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