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M32180F8TFP 参数 Datasheet PDF下载

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型号: M32180F8TFP
PDF下载: 下载PDF文件 查看货源
内容描述: 32位RISC单芯片微型计算机M32R系列M32R / ECU系列 [32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series]
分类和应用: 计算机
文件页数/大小: 839 页 / 3694 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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INTERRUPT CONTROLLER (ICU)  
5.3 Interrupt Request Sources in Internal Peripheral I/O  
5
5.3 Interrupt Request Sources in Internal Peripheral I/O  
The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O,  
A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal  
peripheral I/O is described.  
Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O  
Interrupt Request Sources  
Contents  
Number of  
ICU Type of Input  
Source ( Note 1)  
Input Sources  
TIN3–6 input interrupt request  
TIN3–TIN6 inputs  
4
10  
8
3
5
2
2
1
4
2
6
2
4
5
1
1
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Edge-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
Edge-recognized  
Edge-recognized  
TIN20–29 input interrupt request TIN20–TIN29 inputs  
TIN12–19 input interrupt request TIN12–TIN19 inputs  
TIN0–2 input interrupt request  
TIN0–TIN2 inputs  
TIN7–11 input interrupt request TIN7–TIN11 inputs  
TMS0,1 output interrupt request TMS0, TMS1 output  
TOP8,9 output interrupt request TOP8, TOP9 output  
TOP10 output interrupt request  
TIO4–7 output interrupt request TIO4–TIO7 outputs  
TIO8,9 output interrupt request TIO8, TIO9 outputs  
TOP10 output  
TOP0–5 output interrupt request TOP0–TOP5 outputs  
TOP6,7 output interrupt request TOP6–TOP7 outputs  
TIO0–3 output interrupt request TIO0–TIO3 outputs  
DMA0-4 interrupt request  
DMA0–4 transfer completed  
SIO1 receive interrupt request  
SIO1 transmit interrupt request  
SIO1 reception-completed or receive error interrupt  
SIO1 transmission-completed or transmit buffer empty  
interrupt  
SIO0 receive interrupt request  
SIO0 transmit interrupt request  
SIO0 reception-completed or receive error interrupt  
SIO0 transmission-completed or transmit buffer empty  
interrupt  
1
1
Edge-recognized  
Edge-recognized  
A-D0 conversion interrupt request  
A-D0 converter’s scan mode one-shot operation,  
single mode or comparate mode completed  
TID0 output  
1
Edge-recognized  
TID0 output interrupt request  
TOU0 output interrupt request  
DMA5–9 interrupt request  
1
8
5
4
Edge-recognized  
Level-recognized  
Level-recognized  
Level-recognized  
TOU0_0–TOU0_7 outputs  
DMA5–9 transfer completed  
SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt,  
request  
transmission-completed or transmit buffer empty interrupt  
RTD interrupt generation command  
TID1 output  
RTD interrupt request  
TID1 output interrupt request  
1
1
Edge-recognized  
Edge-recognized  
Level-recognized  
Level-recognized  
TOU1,2 output interrupt request TOU1_0–TOU1_7 outputs, TOU2_0–TOU2_7 outputs 16  
SIO4,5 transmit/receive interrupt SIO4,5 reception-completed or receive error interrupt,  
4
request  
transmission-completed or transmit buffer empty interrupt  
A-D1 converter’s scan mode one-shot operation,  
single mode or comparate mode completed  
TID2 output  
A-D1 conversion interrupt request  
1
Edge-recognized  
TID2 output interrupt request  
1
Edge-recognized  
Level-recognized  
Level-recognized  
TIN30–33 input interrupt request TIN30–TIN33 inputs  
4
CAN0 transmit/receive & error  
interrupt request  
CAN0 transmission or reception completed, CAN0 error  
35  
passive, CAN0 error bus-off, CAN0 bus error, single shot  
CAN1 transmission or reception completed, CAN1 error  
passive, CAN1 error bus-off, CAN1 bus error, single shot  
CAN1 transmit/receive & error  
interrupt request  
35  
Level-recognized  
Note 1: ICU type of input source  
• Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU.  
• Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For  
this type of interrupt, the ICU’s Interrupt Control Register IRQ bit cannot be set or cleared in software.  
32180 Group User’s Manual (Rev.1.0)  
5-11  
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