INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
5
EI (External Interrupt)
vector entry
BRA instruction
H'0000 0080
EI (External Interrupt)
handler
Hardware preprocessing
when EIT is accepted
Save BPC to the stack
(Note 1)
Save PSW to the stack
[1]
Save general-purpose
registers to the stack
Program being
executed
Read and save Interrupt
Request Mask Register
(IMASK) to the stack
IMASK
H'0080 0004
H'0080 0000
[2]
[3]
[4]
Interrupt
generated
Read Interrupt Vector
Register (IVECT)
IVECT
(Note 2)
Read and overwrite
Interrupt Request Mask
Register (IMASK)
(Note 2)
(Note 3)
ICU vector table
Read ICU vector table
[5]
[6]
[7]
H'0000 0094
H'0000 0113
Interrupt handler
start address
Set PSW register IE bit to 1
(Note 4)
(Note 5)
Branch to the interrupt handler
for each internal peripheral I/O
Hardware postprocessing
when RTE instruction
is executed
Interrupt
handler
Interrupt
handler
[8]
(Note 1)
Clear PSW register
IE bit to 0
[9]
(Note 4)
(Note 2)
Restore Interrupt Request
Mask Register (IMASK)
from the stack
[10]
Restore general-purpose
registers from the stack
[1] to [12]: Processing of EI
by interrupt handler
[11]
[12]
Restore PSW from the stack
Restore BPC from the stack
RTE
Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure."
Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK)
in the EIT handler unless interrupts are disabled (PSW register IE bit = 0).
Note 3: When multiple interrupts are disabled, execute processing in [4]. Processing in [4] is unnecessary if multiple
interrupts are enabled by executing processing in [6] and [9].
Note 4: To enable multiple interrupts, execute processing in [6] and [9].
Note 5: To reenable interrupts (by setting the IE bit to 1) after reading the Interrupt Vector Register (IVECT),
perform a dummy access to the internal memory, etc. before reenabling interrupts. In the example here,
there is no need to add a dummy access because the ICU vector table is read after reading the IVECT register.
Similarly, to reenable interrupts (by setting the IE bit to 1) after writing to the Interrupt Request Mask Register
(IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts.
Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O
32180 Group User’s Manual (Rev.1.0)
5-17
RENESAS [ RENESAS TECHNOLOGY CORP ]
