INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers
5
Interrupt request from
each internal peripheral I/O
IREQ Set
F/F
Bit 3 or 11
Data bus
Set/clear
Reset
IVECT read
IMASK write
Interrupt enabled
Clear
Bits 5-7 or bits 13-15
3
ILEVEL
(levels 0-7)
Set
EI
Interrupt priority
resolving circuit
To the CPU core
F/F
Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type)
Interrupt request from each
group internal peripheral I/O
Group interrupt
Read
IREQ
Read-only circuit
Data bus
b3, b11
Reset
IVECT read
IMASK write
Interrupt enabled
Clear
EI
b5-b7, b13-b15
ILEVEL
(levels 0-7)
Set
Interrupt priority
resolving circuit
3
To the CPU core
F/F
Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type)
(2) ILEVEL (Interrupt Priority Level) (Bits 5–7 or bits 13–15)
These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to ‘111’
to disable or any value ‘000’ through ‘110’ to enable the interrupt from some internal peripheral I/O.
When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt
sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether
to forward an EI request to the CPU or keep the interrupt request pending.
The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts
are accepted.
Table 5.2.1 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set
IMASK values at which interrupts are accepted
0 (ILEVEL = "000")
1 (ILEVEL = "001")
2 (ILEVEL = "010")
3 (ILEVEL = "011")
4 (ILEVEL = "100")
5 (ILEVEL = "101")
6 (ILEVEL = "110")
7 (ILEVEL = "111")
Accepted when IMASK is 1–7
Accepted when IMASK is 2–7
Accepted when IMASK is 3–7
Accepted when IMASK is 4–7
Accepted when IMASK is 5–7
Accepted when IMASK is 6–7
Accepted when IMASK is 7
Not accepted (interrupts disabled)
32180 Group User’s Manual (Rev.1.0)
5-10
RENESAS [ RENESAS TECHNOLOGY CORP ]
