M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
th(BCLK-CS)
6ns.min
(0.5×tcyc-10)ns.min
td(BCLK-CS)
40ns.max
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(ALE-AD)
(0.5×tcyc-15)ns.min
ADi
Data input
Address
/DBi
th(RD-DB)
tdZ(RD-AD)
8ns.max
0ns.min
td(BCLK-AD)
40ns.max
tac3(RD-DB)
tsu(DB-RD)
50ns.min
th(BCLK-AD)
4ns.min
td(AD-RD)
0ns.min
(2.5×tcyc-60)ns.max
ADi
BHE
(No multiplex)
td(BCLK-ALE)
40ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
RD
th(BCLK-RD)
0ns.min
td(BCLK-RD)
40ns.max
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
th(BCLK-CS)
4ns.min
td(BCLK-CS)
40ns.max
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
50ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
td(DB-WR)
th(WR-DB)
(0.5×tcyc-40)ns.min
(2.5×tcyc-50)ns.min
(0.5×tcyc-10)ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
(No multiplex)
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
40ns.max
WR, WRL
WRH
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.21
Timing Diagram (9)
Rev.2.41 Jan 10, 2006 Page 81 of 96
REJ03B0001-0241
RENESAS [ RENESAS TECHNOLOGY CORP ]
