M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
30ns.max
th(RD-AD)
0ns.min
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
30ns.max
RD
tac2(RD-DB)
(2.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
th(BCLK-ALE)
-4ns.min
(0.5 × tcyc-10)ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
30ns.max
WR, WRL
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
(0.5 × tcyc-10)ns.min
(1.5 × tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.18
Timing Diagram (6)
Rev.2.41 Jan 10, 2006 Page 78 of 96
REJ03B0001-0241