M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK−AD)
30ns.max
th(BCLK−AD)
4ns.min
ADi
BHE
th(RD−AD)
th(BCLK−ALE)
−4ns.min
td(BCLK−ALE)
0ns.min
30ns.max
ALE
RD
td(BCLK−RD)
30ns.max
th(BCLK−RD)
0ns.min
tac2(RD−DB)
(1.5 × tcyc−60)ns.max
Hi−Z
DBi
th(RD−DB)
0ns.min
tsu(DB−RD)
50ns.min
Write timing
BCLK
td(BCLK−CS)
30ns.max
th(BCLK−CS)
4ns.min
CSi
tcyc
td(BCLK−AD)
30ns.max
th(BCLK−AD)
4ns.min
ADi
BHE
td(BCLK−ALE)
30ns.max
th(BCLK−ALE)
−4ns.min
th(WR−AD)
(0.5 × tcyc−10)ns.min
ALE
td(BCLK−WR)
th(BCLK−WR)
30ns.max
0ns.min
WR,WRL,
WRH
td(BCLK−DB)
th(BCLK−DB)
40ns.max
4ns.min
Hi−Z
DBi
td(DB−WR)
(0.5 × tcyc−40)ns.min
th(WR−DB)
(0.5 × tcyc−10)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.17
Timing Diagram (5)
Rev.2.41 Jan 10, 2006 Page 77 of 96
REJ03B0001-0241