M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.51
A/D Conversion Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ.
Max.
10
−
Resolution
VREF=VCC1
Bits
INL
Integral Non-Linearity
Error
10bit
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
±3
LSB
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
±7
LSB
8bit
VREF=VCC1=5V
±2
±3
LSB
LSB
−
Absolute Accuracy
10bit
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
±7
±2
LSB
8bit
VREF=VCC1=5V
LSB
kΩ
−
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
3
DNL
±1
±3
±3
40
LSB
LSB
LSB
kΩ
−
−
Gain Error
RLADDER
tCONV
Ladder Resistance
VREF=VCC1
10
10-bit Conversion Time, Sample & Hold
Function Available
VREF=VCC1=5V, φAD=12MHz
2.75
µs
tCONV
8-bit Conversion Time, Sample & Hold
Function Available
VREF=VCC1=5V, φAD=12MHz
2.33
µs
tSAMP
VREF
VIA
Sampling Time
0.25
2.0
0
µs
V
Reference Voltage
Analog Input Voltage
VCC1
VREF
V
NOTES:
1. Referenced to VCC1=AVCC=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified.
T version = −40 to 85°C, V version =−40 to 125°C
2. φAD frequency must be 12 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.
When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2.
(1)
Table 5.52
D/A Conversion Characteristics
Standard
Typ.
Symbol
Parameter
Measuring Condition
Unit
Min.
4
Max.
8
−
Resolution
Bits
%
−
Absolute Accuracy
Setup Time
1.0
3
tSU
RO
µs
Output Resistance
Reference Power Supply Input Current
10
20
1.5
kΩ
mA
IVREF
(NOTE 2)
NOTES:
1. Referenced to VCC1=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified. T
version = −40 to 85°C, V version =−40 to 125°C
2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor
ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id
disconnected by the A/D control register.
Rev.2.41 Jan 10, 2006 Page 84 of 96
REJ03B0001-0241