M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.50
Recommended Operating Conditions (1)
Standard
Unit
Symbol
Parameter
Min.
4.0
Typ.
5.0
VCC1
0
Max.
5.5
VCC1, VCC2 Supply Voltage (VCC1 = VCC2)
V
V
V
V
V
AVCC
VSS
Analog Supply Voltage
Supply Voltage
AVSS
VIH
Analog Supply Voltage
0
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
HIGH Input
Voltage (4)
0.8VCC2
0.8VCC2
0.8VCC1
VCC2
VCC2
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
V
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
P7_0, P7_1
0.8VCC1
0
6.5
V
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
VIL
LOW Input
Voltage (4)
0.2VCC2
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0
0
0.2VCC2
0.2VCC
V
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
HIGH Peak
Output Current
(4)
−10.0
−5.0
10.0
5.0
mA
mA
mA
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
HIGH Average
Output Current
(4)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
LOW Peak
Output Current
(4)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
LOW Average
Output Current
(4)
VCC1=4.0V to 5.5V
f(XIN)
Main Clock Input Oscillation Frequency
Sub-Clock Oscillation Frequency
On-chip Oscillation Frequency
PLL Clock Oscillation Frequency
CPU Operation Clock
0
16
50
2
MHz
kHz
MHz
MHz
MHz
ms
f(XCIN)
f(Ring)
f(PLL)
32.768
1
0.5
10
0
VCC1=4.0V to 5.5V
VCC1=5.5V
24
24
20
f(BCLK)
tSU(PLL)
PLL Frequency Synthesizer Stabilization
Wait Time
NOTES:
1. Referenced to VCC1 = VCC2 = 4.7 to 5.5V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified.
T version = −40 to 85 °C, V version= −40 to 125 °C.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10 P1, P14_0 and P14_1 must be 80mA max. The total IOL(peak) for
ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must
be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports P6,
P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and P14_1 must
be −40mA max.
As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS.
4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006 Page 83 of 96
REJ03B0001-0241
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