14.1.1
Block Diagram
Figure 14.1 is a block diagram of the host interface.
(Internal interrupt signals)
IBF2
IBF1
HDB7–HDB0
CS1
ECS2/CS2
IOR
EIOW/IOW
HA0
Control
logic
IDR1
ODR1
STR1
IDR2
Fast
A20
gate
Host
interrupt
request
ODR2
STR2
HICR
control
HIRQ1
HIRQ11
HIRQ12
GA20
Port 4
Port 8
Bus
interface
Internal data bus
Legend:
IDR1: Input data register 1
IDR2: Input data register 2
ODR1: Output data register 1
ODR2: Output data register 2
STR1: Status register 1
STR2: Status register 2
HICR: Host interface control register
Figure 14.1 Host Interface Block Diagram
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