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HD64F3337YF16 参数 Datasheet PDF下载

HD64F3337YF16图片预览
型号: HD64F3337YF16
PDF下载: 下载PDF文件 查看货源
内容描述: 单片机 [Single-Chip Microcomputer]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 747 页 / 2993 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bit 6—Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt  
(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is  
set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER), framing  
error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1.  
Bit 6: RIE  
Description  
0
The receive-end interrupt (RXI) and receive-error (ERI) requests are disabled.  
(Initial value)  
1
The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled.  
Bit 5—Transmit Enable (TE): This bit enables or disables the transmit function. When the  
transmit function is enabled, the TxD pin is automatically used for output. When the transmit  
function is disabled, the TxD pin can be used as a general-purpose I/O port.  
Bit 5: TE  
Description  
0
The transmit function is disabled.  
(Initial value)  
The TxD pin can be used for general-purpose I/O.  
The transmit function is enabled. The TxD pin is used for output.  
1
Bit 4—Receive Enable (RE): This bit enables or disables the receive function. When the receive  
function is enabled, the RxD pin is automatically used for input. When the receive function is  
disabled, the RxD pin is available as a general-purpose I/O port.  
Bit 4: RE  
Description  
0
The receive function is disabled. The RxD pin can be used for general-purpose  
I/O.  
(Initial value)  
1
The receive function is enabled. The RxD pin is used for input.  
Bit 3—Multiprocessor Interrupt Enable (MPIE): When serial data is received in a  
multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receive-  
error interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or  
disables the transfer of received data from RSR to RDR, and enables or disables setting of the  
RDRF, FER, PER, and ORER bits in the serial status register (SSR).  
The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode.  
Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this condition  
data is received regardless of the value of the multiprocessor bit in the receive data.  
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