Item
11.1.1 Features
Page Revisions (See Manual for Details)
191 to Description amended
193 Prescaler
1/1 to 1/32 clock scaling possible in initial stage for
channels 0 to 8, 10, and 11
Channels 1 to 5 enable TI10 pin input, multiple the
TI10 pin input (correction), and select AGCK and
AGCKM.
Channel 2
Provision for forcible cutoff of channel 8 down-
counters(DCNT8I to P)
Channel 8
Reload function can be set to eight 16-bit down
counters (DCNT8I to DCNT8P)
Channel 9
•
Channel 9 has six event counters and six general
registers, allowing the following operations:
Channel 10 has a 32-bit output compare and input
capture register, free-running counter, 16-bit free-
running counter, output compare/input capture
register, reload register, 8-bit event counter, and
output compare register, and one 16-bit reload
counter, allowing the following operations:
Reload count possible with 1/32, 1/64, 1/128, or
1/256 times the captured value
Channel 11
Waveform output at compare match: 0 output, 1
output, and toggle output selectable
Input capture function: Detection at rising edge,
falling edge, and both edges
Compare-match signal can be output at the APC
by using a general register as a output compare
register
Channel 10
•
Rev.2.0, 07/03, page ix of xxxviii
RENESAS [ RENESAS TECHNOLOGY CORP ]
