Item
11.1.1 Features
Table 11.1 ATU-II functions
Page Revisions (See Manual for Details)
195, Table amended
196
Channel 1
(φ–φ/32)
×
(1/2n)
(n = 0–5)
TCLKA, TCLKB,
AGCK, AGCKM
Channel 2
(φ–φ/32)
×
(1/2n)
(n = 0–5)
TCLKA, TCLKB,
AGCK, AGCKM
Channels 3–5
(φ–φ/32)
×
(1/2n)
(n = 0–5)
TCLKA, TCLKB,
AGCK, AGCKM
GR10G
OCR10AH,
OCR10AL,
OCR10B,
NCR10,
TCCLR10
11.1.3 Register Configuration
Table 11.3 ATU-II Registers
201
Table amended
TSTR1
TSTR2
TSTR3
PSCR1
PSCR2
PSCR3
PSCR4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
H'00
H'00
H'00
H'00
H'00
H'00
H'00
11.2.2 Prescaler
Registers(PSCR)
227
Bit Table amended
Bit:
7
—
Initial value:
R/W:
x = 1 to 4
0
R
6
—
0
R
5
—
0
R
4
PSCxE
0
R/W
3
PSCxD
0
R/W
2
PSCxC
0
R/W
1
PSCxB
0
R/W
0
PSCxA
0
R/W
11.2.4 Timer I/O Control
Registers(TIOR)
Timer I/O Control Registers 3A,
3B, 4A, 4B, 5A, 5B(TIOR3A,
TIOR3B, TIOR4A, TIOR4B,
TIOR5A, TIOR5B)
246, Table amended
247 Bits 6 to 4
1
0
0
1
1
0
GR is an input
capture register
(input capture by
channel 3 and 9
compare-match
enabled)
Input capture disabled (In channel 3
only, GR cannot be written to)
Input capture in GR on rising edge at
TIOxx pin (GR cannot be written to)
Input capture in GR on falling edge at
TIOxx pin (GR cannot be written to)
Bits 2 to 0
1
0
0
1
1
0
GR is an input
capture register
(input capture by
channel 3 and 9
compare-match
enabled)
Input capture disabled (In channel 3
only, GR cannot be written to)
Input capture in GR on rising edge at
TIOxx pin (GR connot be written to)
Input capture in GR on falling edge at
TIOxx pin (GR connot be written to)
Rev.2.0, 07/03, page x of xxxviii
RENESAS [ RENESAS TECHNOLOGY CORP ]
