Item
Page Revisions (See Manual for Details)
797 Table amended and added
Minimum Interval
22.8.3 Other Notes
2. User branch processing
intervals
Approximately 19 µs
Table 22.11 Initiation Intervals
of User Branch Processing
Approximately 19 µs
Processing
Programming
Erasing
Max.
Min.
Table 22.12 Required Period for
Initiating User Branch Processing
Approximately 113 µs
Approximately 85 µs
Approximately 113 µs
Approximately 45 µs
4. State in which AUD operation
is disabled and interrupts are
ignored
Description added
Checking the flash-memory related registers
immediately after user boot mode is initiated
(Approximately 100 µs when operation with
internal frequency of 40 MHz is carried out after
the reset signal is released.)
22.10.1 Serial Communication 827 Description added
Interface Specification for Boot
Mode
Command:
Read start address (four bytes): Size of data to be read
(3) Memory read
Error response:
H’2A: Address error
The start address for reading is not in the MAT.
H’2B: Size error
The read size exceeds the MAT, the last address
for reading calculated from the start address for
reading and the read size is not in the MAT, or
read size is 0.
24.3.1 Transition to Hardware 854 Description added
Standby Mode
The chip enters hardware standby mode when the HSTBY
and RES pins go low. Set the pins following to mode
setup pin shown in section 4, Operating modes. Operation
with other pin set up are not guaranteed.
Hardware standby mode reduces power consumption
drastically by halting all SH7055SF functions
Rev.2.0, 07/03, page xiv of xxxviii
RENESAS [ RENESAS TECHNOLOGY CORP ]
