Appendix
Addressing Mode and
Instruction Length (bytes)
No. of
States*1
Condition Code
Mnemonic
Operation
I
H
N
Z
V
C
NEG.B Rd
B
W
L
2
2
2
2
0–Rd8 → Rd8
—
—
—
—
2
2
2
2
NEG
NEG.W Rd
NEG.L ERd
0–Rd16 → Rd16
0–ERd32 → ERd32
EXTU EXTU.W Rd
W
0 → (<bits 15 to 8>
of Rd16)
—
—
—
—
0
0
0
0
0
0
—
—
—
—
EXTU.L ERd
L
W
L
2
2
2
0 → (<bits 31 to 16>
of ERd32)
—
—
—
2
2
2
EXTS EXTS.W Rd
EXTS.L ERd
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
Rev. 3.00 Sep. 10, 2007 Page 465 of 528
REJ09B0216-0300