Section 17 I2C Bus Interface 2 (IIC2)
Section 17 I2C Bus Interface 2 (IIC2)
The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus)
interface functions. The register configuration that controls the I2C bus differs partly from the
Philips configuration, however.
Figure 17.1 shows a block diagram of the I2C bus interface 2.
Figure 17.2 shows an example of I/O pin connections to external circuits.
17.1
Features
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•
Selection of I2C format or clock synchronous serial format
Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
I2C bus format
•
•
•
•
Start and stop conditions generated automatically in master mode
Selection of acknowledge output levels when receiving
Automatic loading of acknowledge bit when transmitting
Bit synchronization/wait function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
•
•
Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
Direct bus drive
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Clock synchronous format
•
Four interrupt sources
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
IFIIC10A_000020020200
Rev. 3.00 Sep. 10, 2007 Page 329 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
