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HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
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内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
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文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 16 Serial Communication Interface 3 (SCI3)  
16.7  
Interrupts  
SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive  
data full, and receive errors (overrun error, framing error, and parity error). Table 16.7 shows the  
interrupt sources.  
Table 16.7 SCI3 Interrupt Requests  
Interrupt Requests  
Receive Data Full  
Transmit Data Empty  
Transmission End  
Receive Error  
Abbreviation  
Interrupt Sources  
RXI  
TXI  
TEI  
ERI  
Setting RDRF in SSR  
Setting TDRE in SSR  
Setting TEND in SSR  
Setting OER, FER, and PER in SSR  
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before  
transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data  
is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is  
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if  
the transmit data has not been sent. It is possible to make use of the most of these interrupt  
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the  
generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that  
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.  
Rev. 3.00 Sep. 10, 2007 Page 325 of 528  
REJ09B0216-0300  
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