Section 17 I2C Bus Interface 2 (IIC2)
Transfer clock
generation
circuit
Transmission/
reception
control circuit
ICCR1
ICCR2
ICMR
Output
control
SCL
Noise canceler
ICDRT
SAR
Output
control
ICDRS
SDA
Address
comparator
Noise canceler
ICDRR
Bus state
decision circuit
Arbitration
decision circuit
ICSR
ICIER
Interrupt
generator
Interrupt request
[Legend]
ICCR1: I2C bus control register 1
ICCR2: I2C bus control register 2
ICMR: I2C bus mode register
ICSR: I2C bus status register
ICIER: I2C bus interrupt enable register
ICDRT: I2C bus transmit data register
ICDRR: I2C bus receive data register
ICDRS: I2C bus shift register
SAR:
Slave address register
Figure 17.1 Block Diagram of I2C Bus Interface 2
Rev. 3.00 Sep. 10, 2007 Page 330 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
