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HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
PDF下载: 下载PDF文件 查看货源
内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
分类和应用:
文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 16 Serial Communication Interface 3 (SCI3)  
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,  
FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.13 shows a sample flow  
chart for serial data reception.  
Start reception  
[1] Read the OER flag in SSR to determine if  
there is an error. If an overrun error has  
[1]  
occurred, execute overrun error processing.  
[2] Read SSR and check that the RDRF flag is  
set to 1, then read the receive data in RDR.  
When data is read from RDR, the RDRF  
flag is automatically cleared to 0.  
Read OER flag in SSR  
Yes  
OER = 1  
No  
[4]  
[3] To continue serial reception, before the  
MSB (bit 7) of the current frame is received,  
reading the RDRF flag and reading RDR  
should be finished. When data is read from  
RDR, the RDRF flag is automatically  
cleared to 0.  
Error processing  
(Continued below)  
Read RDRF flag in SSR  
[2]  
[4] If an overrun error occurs, read the OER  
flag in SSR, and after performing the  
appropriate error processing, clear the OER  
flag to 0. Reception cannot be resumed if  
the OER flag is set to 1.  
No  
RDRF = 1  
Yes  
Read receive data in RDR  
Yes  
All data received?  
No  
[3]  
Clear RE bit in SCR3 to 0  
<End>  
[4]  
Error processing  
Overrun error processing  
Clear OER flag in SSR to 0  
<End>  
Figure 16.13 Sample Serial Reception Flowchart (Clock Synchronous Mode)  
Rev. 3.00 Sep. 10, 2007 Page 315 of 528  
REJ09B0216-0300  
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