Section 16 Serial Communication Interface 3 (SCI3)
16.5.4
Serial Data Reception (Clock Synchronous Mode)
Figure 16.12 shows an example of SCI3 operation for reception in clock synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronization clock input or
output, starts receiving data.
2. The SCI3 stores the receive data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
1 frame
RDRF
OER
LSI
RXI interrupt RDRF flag
RXI interrupt request generated
ERI interrupt request
operation
request
generated
cleared
to 0
generated by
overrun error
User
processing
RDR data read
RDR data has
not been read
(RDRF = 1)
Overrun error
processing
Figure 16.12 Example of SCI3 Reception in Clock Synchronous Mode
Rev. 3.00 Sep. 10, 2007 Page 314 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
