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HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
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内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
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文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 16 Serial Communication Interface 3 (SCI3)  
16.5  
Operation in Clock Synchronous Mode  
Figure 16.9 shows the general format for clock synchronous communication. In clock synchronous  
mode, data is transmitted or received synchronous with clock pulses. A single character in the  
transmit data consists of the 8-bit data starting from the LSB. In clock synchronous serial  
communication, data on the transmission line is output from one falling edge of the  
synchronization clock to the next. In clock synchronous mode, the SCI3 receives data in  
synchronous with the rising edge of the synchronization clock. After 8-bit data is output, the  
transmission line holds the MSB state. In clock synchronous mode, no parity or multiprocessor bit  
is added. Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex  
communication through the use of a common clock. Both the transmitter and the receiver also  
have a double-buffered structure, so data can be read or written during transmission or reception,  
enabling continuous data transfer.  
8 bits  
One unit of transfer data (character or frame)  
*
*
Synchronization  
clock  
LSB  
Bit 0  
MSB  
Bit 7  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Serial data  
Don’t care  
Note: * High except in continuous transfer  
Don’t care  
Figure 16.9 Data Format in Clock Synchronous Communication  
16.5.1 Clock  
Either an internal clock generated by the on-chip baud rate generator or an external  
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM  
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,  
the synchronization clock is output from the SCK3 pin. Eight synchronization clock pulses are  
output in the transfer of one character, and when no transfer is performed the clock is fixed high.  
16.5.2  
SCI3 Initialization  
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample  
flowchart in figure 16.4.  
Rev. 3.00 Sep. 10, 2007 Page 311 of 528  
REJ09B0216-0300  
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