Section 16 Serial Communication Interface 3 (SCI3)
16.4.4
Serial Data Reception
Figure 16.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI3 operates as described below.
1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
Start
bit
Receive
data
Parity Stop Start
Receive
data
Parity Stop Mark state
bit
bit bit
bit
bit
(idle state)
Serial
data
1
0
D0 D1
D7 0/1
1
0
D0 D1
1 frame
D7 0/1
0
1
1 frame
RDRF
FER
LSI
operation
RXI request RDRF
cleared to 0
0 stop bit
detected
ERI request in
response to
framing error
User
processing
RDR data read
Framing error
processing
Figure 16.7 Example of SCI3 Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev. 3.00 Sep. 10, 2007 Page 307 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
