Section 13 Timer Z
13.3.9
Timer Control Register (TCR)
The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and
counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Initial
Bit
7
Bit Name value
R/W
R/W
R/W
R/W
Description
CCLR2
CCLR1
CCLR0
0
0
0
Counter Clear 2 to 0
000: Disables TCNT clearing
6
5
001: Clears TCNT by GRA compare match/input
capture*1
010: Clears TCNT by GRB compare match/input
capture*1
011: Synchronization clear; Clears TCNT in synchronous
with counter clearing of the other channel’s timer*2
100: Disables TCNT clearing
101: Clears TCNT by GRC compare match/input
capture*1
110: Clears TCNT by GRD compare match/input
capture*1
111: Synchronization clear; Clears TCNT in synchronous
with counter clearing of the other channel’s timer*2
4
3
CKEG1
CKEG0
0
0
R/W
R/W
Clock Edge 1 and 0
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 2 to 0
000: Internal clock: count by φ
001: Internal clock: count by φ/2
010: Internal clock: count by φ/4
011: Internal clock: count by φ/8
1XX: External clock: count by FTIOA0 (TCLK) pin input
Notes: 1. When GR functions as an output compare register, TCNT is cleared by compare match.
When GR functions as input capture, TCNT is cleared by input capture.
2. Synchronous operation is set by TMDR.
3. X: Don’t care
Rev. 3.00 Sep. 10, 2007 Page 214 of 528
REJ09B0216-0300
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