Section 13 Timer Z
13.3.11 Timer Status Register (TSR)
TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture
of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a
corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers,
one for each channel.
Initial
Bit
Bit Name value
R/W
Description
7, 6
All 1
0
Reserved
These bits are always read as 1.
Underflow Flag
5
4
3
UDF*
R/W
R/W
R/W
[Setting condition]
•
When TCNT_1 underflows
[Clearing condition]
When 0 is written to UDF after reading UDF = 1
•
OVF
0
0
Overflow Flag
[Setting condition]
•
When the TCNT value underflows
[Clearing condition]
When 0 is written to OVF after reading OVF = 1
•
IMFD
Input Capture/Compare Match Flag D
[Setting conditions]
•
When TCNT = GRD and GRD is functioning as output
compare register
•
When TCNT value is transferred to GRD by input
capture signal and GRD is functioning as input
capture register
[Clearing condition]
When 0 is written to IMFD after reading IMFD = 1
•
Rev. 3.00 Sep. 10, 2007 Page 218 of 528
REJ09B0216-0300
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