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HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
PDF下载: 下载PDF文件 查看货源
内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
分类和应用:
文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 13 Timer Z  
Initial  
Bit  
Bit Name Value  
R/W  
Description  
3
OLS1  
0
R/W  
Output Level Select 1  
Selects the counter-phase output levels in reset  
synchronous PWM mode or complementary PWM mode.  
0: Initial output is high and the active level is low.  
1: Initial output is low and the active level is high.  
Output Level Select 0  
2
OLS0  
0
R/W  
Selects the normal-phase output levels in reset  
synchronous PWM mode or complementary PWM mode.  
0: Initial output is high and the active level is low.  
1: Initial output is low and the active level is high.  
Figure 13.4 shows an example of outputs in reset  
synchronous PWM mode and complementary PWM  
mode when OLS1 = 0 and OLS0 = 0.  
1
0
CMD1  
CMD0  
0
0
R/W  
R/W  
Combination Mode 1 and 0  
00: Channel 0 and channel 1 operate normally  
01: Channel 0 and channel 1 are used together to  
operate in reset synchronous PWM mode  
10: Channel 0 and channel 1 are used together to  
operate in complementary PWM mode (transferred at  
the trough)  
11: Channel 0 and channel 1 are used together to  
operate in complementary PWM mode (transferred at  
the crest)  
Note: When reset synchronous PWM mode or  
complementary PWM mode is selected by these  
bits, this setting has the priority to the settings for  
PWM mode by each bit in TPMR. Stop TCNT_0  
and TCNT_1 before making settings for reset  
synchronous PWM mode or complementary PWM  
mode.  
Rev. 3.00 Sep. 10, 2007 Page 209 of 528  
REJ09B0216-0300  
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