Section 13 Timer Z
FTIOA1
FTIOB1
FTIOC1
FTIOD1
φ, φ/2,
φ/4, φ/8
Clock select
Comparator
Control logic
ITMZ1
Module data bus
[Legend]
TCNT_1:
Timer counter_1 (16 bits)
GRA_1, GRB_1, General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers:
GRC_1, GRD_1: 16 bits × 4)
TCR_1:
Timer control register_1 (8 bits)
TIORA_1:
TIORC_1:
TSR_1:
Timer I/O control register A_1 (8 bits)
Timer I/O control register C_1 (8 bits)
Timer status register_1 (8 bits)
TIER_1:
POCR_1:
ITMZ1:
Timer interrupt enable register_1 (8 bits)
PWM mode output level control register_1 (8 bits)
Channel 1 interrupt
Figure 13.3 Timer Z (Channel 1) Block Diagram
Rev. 3.00 Sep. 10, 2007 Page 203 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
