Section 13 Timer Z
ITMZ0
ITMZ1
FTIOA0
FTIOB0
FTIOC0
FTIOD0
Control logic
FTIOA1
FTIOB1
FTIOC1
FTIOD1
φ, φ/2,
φ/4, φ/8
ADTRG
TSTR
TPMR
TOER
TMDR
TFCR
TOCR
Channel 0
timer
Channel 1
timer
Module data bus
[Legend]
TSTR: Timer start register (8 bits)
TMDR: Timer mode register (8 bits)
TPMR: Timer PWM mode register (8 bits)
TFCR: Timer function control register (8 bits)
TOER: Timer output master enable register (8 bits)
TOCR: Timer output control register (8 bits)
ADTRG: A/D conversion start trigger output signal
ITMZ0: Channel 0 interrupt
ITMZ1: Channel 1 interrupt
Figure 13.1 Timer Z Block Diagram
Rev. 3.00 Sep. 10, 2007 Page 201 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
