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HD64F36077G 参数 Datasheet PDF下载

HD64F36077G图片预览
型号: HD64F36077G
PDF下载: 下载PDF文件 查看货源
内容描述: 旧公司名称在产品目录等资料 [Old Company Name in Catalogs and Other Documents]
分类和应用:
文件页数/大小: 566 页 / 3220 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Section 13 Timer Z  
Eleven interrupt sources  
Four compare match/input capture interrupts and an overflow interrupt are available for  
each channel. An underflow interrupt can be set for channel 1.  
Table 13.1 Timer Z Functions  
Item  
Channel 0  
Channel 1  
Count clock  
Internal clocks: φ, φ/2, φ/4, φ/8  
External clock: FTIOA0 (TCLK)  
General registers  
(output compare/input  
capture registers)  
GRA_0, GRB_0, GRC_0, GRD_0 GRA_1, GRB_1, GRC_1, GRD_1  
Buffer register  
I/O pins  
GRC_0, GRD_0  
GRC_1, GRD_1  
FTIOA0, FTIOB0, FTIOC0,  
FTIOD0  
FTIOA1, FTIOB1, FTIOC1,  
FTIOD1  
Counter clearing function Compare match/input capture of Compare match/input capture of  
GRA_0, GRB_0, GRC_0, or  
GRD_0  
GRA_1, GRB_1, GRC_1, or  
GRD_1  
Compare  
match output  
0 output  
1 output  
output  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Input capture function  
Synchronous operation  
PWM mode  
Reset synchronous PWM  
mode  
Yes  
Yes  
Yes  
Yes  
Complementary PWM  
mode  
Buffer function  
Interrupt sources  
Compare match/input capture A0 Compare match/input capture A1  
to D0  
to D1  
Overflow  
Overflow  
Underflow  
Rev. 3.00 Sep. 10, 2007 Page 200 of 528  
REJ09B0216-0300  
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